When routing signal carriers for parallel interfaces, such as electrically conducting printed circuit board traces, the spacing between the signal carriers is generally uniform throughout a portion of an interface whereat those signal carriers run physically parallel to one another. For parallel synchronous busses, where data is divided among of the signal carriers of the parallel interface and transmitted at the same time (e.g., in accordance with a clock signal), crosstalk interference among the signal carriers may become significant to the point of reduction of data throughput capabilities. Because a parallel synchronous bus requires the simultaneous transmission of data along all of the signal carriers of the bus, the signal carrier most affected by interference imposes an upper limit on the maximum transmission speed of the entire bus.
The description above is presented as a general overview of related art in this field and should not be construed as an admission that any of the information it contains constitutes prior art against the present patent application.